Clock signals are commonly used in many electronic circuits and for various purposes. A clock signal may continually transition between a logic high and a logic low. The clock signal may have a duty cycle that is determined by the time duration at a logic high and the time duration at a logic low. In some circumstances, it may be desirable to generate the clock signal to have a duty cycle that is approximately equal or equal to 50%, so that the logic high duration is close to the logic low duration. A digital circuit may use both the rising and falling edges of the clock signal to trigger synchronous circuits to achieve faster operating speed. A 50% duty cycle for the clock signal may then provide the synchronous circuits with maximum timing margins.
The duty cycle of a clock signal may be distorted due to various phenomena such as mismatches in transistor devices used to generate the clock signal. Great care is often used in designing clock generation and distribution circuits to minimize device mismatches. Unfortunately, as device size shrinks in advanced integrated circuit (IC) process technologies, duty cycle distortion due to random variations and device mismatches becomes worse. Furthermore, digital circuits fabricated with advanced IC processes typically operate at high speed, e.g., one gigahertz (GHz) or higher. The high speed corresponds to a smaller clock period, e.g., 1 nanosecond (nsec) for 1 GHz. Small circuit mismatches may then translate to a relatively large error in duty cycle with the smaller clock period.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.